Receive Interrupt Enable Bit Description - Freescale Semiconductor MCF5329 Reference Manual

Synchronous Serial Interface (SSI)
The SSI_RCR[RXEXT] bit controls receive data extension. Transmit data used with lsb alignment has no
concept of sign/zero-extension. Unused bits above the most significant bit are simply ignored.
2
When configured in I S or AC97 mode, the SSI forces the lsb alignment. However, the
SSI_RCR[RXEXT] bit chooses zero-extension or sign-extension.
Refer to Section 24.3.10, "SSI Transmit Configuration Register (SSI_TCR),"
Receive Configuration Register (SSI_RCR),"
SSI_RCR registers.
24.4.5

Receive Interrupt Enable Bit Description

If the receive FIFO is not enabled, an interrupt occurs when the corresponding SSI receive data ready
(SSI_ISR[RDR0/1]) bit is set. If the receive FIFO is enabled and the RIE and RE bit are set, the processor
is interrupted when either of the SSI receives FIFO full (SSI_ISR[RFF0/1]) bits is set. When the receive
FIFO is enabled, a maximum of eight values are available to be read (eight values per channel in
two-channel mode). If not enabled, one value can be read from the SSI_RX register (one each in
two-channel mode).
If the RIE bit is cleared, these interrupts are disabled. However, the RFF0/1 and RDR0/1 bits indicate the
receive data register full condition. Reading the SSI_RX registers clears the RDR bits, thus clearing the
pending interrupt. Two receive data interrupts (two per channel in two-channel mode) are available:
receive data with exception status and receive data without exception.
these interrupts are generated.
Receive Data 0 (with exception status)
Receive Data 0 (without exception)
Receive Data 1 (with exception status)
Receive Data 1 (without exception)
24.4.6 Transmit Interrupt Enable Bit Description
The SSI transmit interrupt enable (TIE) bit controls interrupts for the SSI transmitter. If the transmit FIFO
is enabled and the TIE and TE bits are set, the processor is interrupted when either of the SSI transmit FIFO
empty (SSI_ISR[TFE0/1]) flags is set. If the corresponding transmit FIFO is not enabled, an interrupt is
generated when the corresponding SSI_ISR[TDE0/1] flag is set and transmit enable (TE) bit is set.
When transmit FIFO 0 is enabled, a maximum of eight values can be written to the SSI (eight per channel
in two-channel mode using Tx FIFO 1). If not enabled, then one value can be written to the SSI_TX0
register (one per channel in two-channel mode using SSI_TX1). When the TIE bit is cleared, all transmit
interrupts are disabled. However, the TDE0/1 bits always indicate the corresponding SSI_TX register
24-48
for more detail on the relevant bits in the SSI_TCR and
Table 24-25. SSI Receive Data Interrupts
Interrupt
Receive Data 0 Interrupts (n = 0)
Receive Data 1 Interrupts (n = 1)
MCF5329 Reference Manual, Rev 3
and
Table 24-25
RIE ROEn RFFn/RDRn
1 1
1 0
1 1
1 0
Section 24.3.11, "SSI
shows the conditions
1
1
1
1
Freescale Semiconductor