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FlexCAN
23.3.17 Time Stamp
The value of TIMER is sampled at the beginning of the identifier field on the CAN bus. For a message
being received, the time stamp is stored in the TIMESTAMP entry of the receive message buffer at the
time the message is written into that buffer. For a message being transmitted, the TIMESTAMP entry is
written into the transmit message buffer after the transmission has completed successfully.
The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This
feature allows network time synchronization to be performed. See the CANCTRL[TSYN] bit.
23.3.18 Bit Timing
The FlexCAN module CANCTRL register configures the bit timing parameters required by the CAN
protocol. The CLK_SRC, PRESDIV, RJW, PSEG1, PSEG2, and the PROPSEG fields allow the user to
configure the bit timing parameters.
The CANCTRL[CLK_SRC] bit defines whether the module uses the internal bus clock or the output of
the crystal oscillator via the EXTAL pin. The crystal oscillator clock should be selected when a tight
tolerance (up to 0.1%) is required for the CAN bus timing. The crystal oscillator clock has better jitter
performance than PLL generated clocks. The value of this bit should not be changed, unless the module is
in disable mode (CANMCR[MDIS] bit is set)
The PRESDIV field controls a prescaler that generates the serial clock (S-clock), whose period defines the
time quantum used to compose the CAN waveform. A time quantum is the atomic unit of time managed
by the CAN engine.
Internal Bus Clock
(f
sys/3
Oscillator Clock (EXTAL)
A bit time is subdivided into three segments
•
SYNC_SEG: Has a fixed length of one time quantum. Signal edges are expected to happen within
this section.
•
Time Segment 1: Includes the propagation segment and the phase segment 1 of the CAN standard.
It can be programmed by setting the PROPSEG and the PSEG1 fields of the CANCTRL register
so that their sum (plus 2) is in the range of 4 to 16 time quanta.
•
Time Segment 2: Represents the phase segment 2 of the CAN standard. It can be programmed by
setting the PSEG2 field of the CANCTRL register (plus 1) to be 2 to 8 time quanta long.
1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch
CAN 2.0A/B protocol specification dated September 1991 for bit timing.
23-26
CANCTRL[CLK_SRC]
)
1
0
Figure 23-14. CAN Engine Clocking Scheme
f
or EXTAL
sys 3 ⁄
---------------------------------------- -
f
=
(
Tq
PRESDIV + 1
1
(see
-------------------------------------------------------------
Bit Rate
=
(number of Time Quanta)
MCF5329 Reference Manual, Rev 3
Prescaler
(1 .. 256)
)
Figure 23-15
and
Table
23-14):
f
Tq
S clock
Eqn. 23-6
Eqn. 23-7
Freescale Semiconductor
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