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Symmetric Key Hardware Accelerator (SKHA)
35.3.1
Transmit FIFO Interface Block
This block translates the internal FIFO control signals to the input FIFO and passes the message data to
the SKHA logic block. The SKHA logic block continues to pop data from the input FIFO until the FIFO
is empty.
For AES, four 32-bit words are required to process a block. For DES/3DES, two 32-bit words are required
to process a block. During the last word of the FIFO, the SKHA logic does not pop from the FIFO unless
the SKCMR[GO] bit is set, indicating that the host has loaded all the message data.
35.3.2
Receive FIFO Interface Block
This block translates the internal FIFO control signals to the output FIFO and pass the processed message
data from the SKHA logic block. The SKHA logic block pushes the same number of words to the output
FIFO as it pops from the input FIFO. The SKHA logic block pushes to the output FIFO as long as the FIFO
is not full. After the last word is pushed to the output FIFO, the done interrupt is asserted.
35.3.3
Top Control Block
This block generates the input and output FIFO transmit, receive and request signals and translates other
internal signals at the top level.
35-16
Internal Bus
Top Control
Input FIFO
Output FIFO
Transmit
SKHA Logic
Internal Bus Interface
Internal Bus
Figure 35-20. SKHA Block Diagram
MCF5329 Reference Manual, Rev 3
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Freescale Semiconductor
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