Freescale Semiconductor MCF5329 Reference Manual page 462

Universal Serial Bus Interface – On-The-Go Module
Field
31–17 Reserved, must be cleared.
16 NAK interrupt. Set by hardware for a particular endpoint when the TX/RX endpoint's NAK bit and the
NAKI corresponding TX/RX endpoint's NAK enable bit are set. The hardware automatically clears this bit when all
the enabled TX/RX endpoint NAK bits are cleared.
15 Asynchronous schedule status. Reports the current real status of asynchronous schedule. Controller is not
AS immediately required to disable or enable the asynchronous schedule when software transitions the
USBCMD[ASE] bit. When this bit and the USBCMD[ASE] bit have the same value, the asynchronous schedule
is enabled (1) or disabled (0). Used only in host mode.
0 Disabled.
1 Enabled.
14 Periodic schedule status. Reports current real status of periodic schedule. Controller is not immediately
PS required to disable or enable the periodic schedule when software transitions the USBCMD[PSE] bit. When this
bit and the USBCMD[PSE] bit have the same value, the periodic schedule is enabled or disabled. Used only in
host mode.
0 Disabled.
1 Enabled.
13 Reclamation. DetectS an empty asynchronous schedule. Used only by the host mode.
RCL 0 Non-empty asynchronous schedule.
1 Empty asynchronous schedule.
12 Host controller halted. This bit is cleared when the USBCMD[RS] bit is set. The controller sets this bit after it
HCH stops executing because of the USBCMD[RS] bit being cleared, by software or the host controller hardware (for
example, internal error). Used only in host mode.
0 Running.
1 Halted.
11 Reserved, must be cleared.
10 ULPI interrupt. Set by event completion. Present only in the OTG module.
ULPII
9 Reserved, must be cleared.
8 Device-controller suspend. Non-EHCI bit present on the USB OTG module only. When a device controller
SLI enters a suspend state from an active state, this bit is set. The device controller clears the bit upon exiting from
a suspend state. Used only by the device controller.
0 Active.
1 Suspended.
7 SOF received. This is a non-EHCI status bit. Software writes a 1 to this bit to clear it.
SRI Host mode (USB host and USB OTG):
In host mode, this bit is set every 125 μs, provided PHY clock is present and running (for example, the port
is NOT suspended) and can be used by the host-controller driver as a time base.
Device mode (USB OTG-only):
When controller detects a start of (micro) frame, bit is set. When a SOF is extremely late, controller
automatically sets this bit to indicate an SOF was expected. Therefore, this bit is set roughly every 1 ms in
device FS mode and every 125 μsec in HS mode, and it is synchronized to the actual SOF received.
Because the controller is initialized to FS before connect, this bit is set at an interval of 1 ms during the
prelude to the connect and chirp.
21-20
Table 21-18. USBSTS Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor