Freescale Semiconductor MCF5329 Reference Manual page 104

ColdFire Core
3.3.5.7 Branch Instruction Execution Times
Opcode <EA>
Rn
BRA —
BSR —
JMP <ea> —
JSR <ea> —
RTE —
RTS —
Opcode
Bcc
Opcode
Bcc
The following notes apply to the branch execution times:
1. For BRA and JMP <ea> instructions, where <ea> is (d16,PC) or xxx.wl, the branch acceleration
logic of the IFP calculates the target address and begins prefetching the new path. Because the IFP
and OEP are decoupled by the FIFO instruction buffer, the execution time can vary from one to
three cycles, depending on the decoupling amount.
For all other <ea> values of the JMP instruction, the branch acceleration logic is not used, and the
execution times are fixed.
2. For BSR and JSR xxx.wl opcodes, the same branch acceleration mechanism is used to initiate the
fetch of the target instruction. Depending on the amount of decoupling between the IFP and OEP,
the resulting execution times can vary from 1 to 3 cycles.
For the remaining <ea> values for the JSR instruction, the branch acceleration logic is not used,
and the execution times are fixed.
3. For conditional branch opcodes (bcc), a static algorithm is used to determine the prediction state
of the branch. This algorithm is:
if bcc is a forward branch
if CCR[P] == 0
3-30
Table 3-18. General Branch Instruction Execution Times
(An) (An)+
— —
— —
5(0/0) —
5(0/1) —
— 14(2/0)
— 8(1/0)
Table 3-19. Bcc Instruction Execution Times, CCR[P]=0
Forward Forward
Taken Not Taken
5(0/0) 1(0/0)
Table 3-20. Bcc Instruction Execution Times, CCR[P]=1
Predicted Correctly
as Taken
1(0/0)
MCF5329 Reference Manual, Rev 3
Effective Address
(d16,An) (d8,An,Xi*SF)
-(An)
(d16,PC) (d8,PC,Xi*SF)
1
— 1(0/1)
2
— 1(0/1)
1
— 5(0/0) 6(0/0)
— 5(0/1) 6(0/1)
— —
— —
Backward
Taken
3
1(0/0)
Predicted Correctly Predicted
as Not Taken Incorrectly
1(0/0)
xxx.wl #xxx
— — —
— — —
1
1(0/0) —
2
1(0/1) —
— — —
— — —
Backward
Not Taken
5(0/0)
3
5(0/0)
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