Freescale Semiconductor MCF5329 Reference Manual page 14

Paragraph
Number
16.8.1 eDMA Initialization ..................................................................................................... 16-28
16.8.2 DMA Programming Errors .......................................................................................... 16-31
16.8.3 DMA Arbitration Mode Considerations ...................................................................... 16-31
16.8.4 DMA Transfer.............................................................................................................. 16-32
16.8.5 eDMA TCD
16.8.6 Channel Linking .......................................................................................................... 16-36
16.8.7 Dynamic Programming................................................................................................ 16-37
17.1 Introduction .................................................................................................................................. 17-1
17.1.1 Overview........................................................................................................................ 17-1
17.1.2 Features .......................................................................................................................... 17-2
17.2 External Signals............................................................................................................................ 17-2
17.2.1 Address and Data Buses (FB_A[23:0], FB_D[31:0])................................................... 17-2
17.2.2 Chip Selects (FB_CS[5:0]) ............................................................................................ 17-3
17.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0]) ................................................ 17-3
17.2.4 Output Enable (FB_OE) ................................................................................................ 17-3
17.2.5 Read/Write (FB_R/W) ................................................................................................... 17-3
17.2.6 Transfer Start (FB_TS) .................................................................................................. 17-3
17.2.7 Transfer Acknowledge (FB_TA)................................................................................... 17-3
17.3 Memory Map/Register Definition................................................................................................ 17-4
17.3.1 Chip-Select Address Registers (CSAR0 - CSAR5) ...................................................... 17-4
17.3.2 Chip-Select Mask Registers (CSMR0 - CSMR5) ......................................................... 17-5
17.3.3 Chip-Select Control Registers (CSCR0 - CSCR5) ....................................................... 17-6
17.4 Functional Description ................................................................................................................. 17-9
17.4.1 Chip-Select Operation.................................................................................................... 17-9
17.4.2 Data Transfer Operation .............................................................................................. 17-10
17.4.3 Data Byte Alignment and Physical Connections ......................................................... 17-11
17.4.4 Bus Cycle Execution.................................................................................................... 17-12
17.4.5 FlexBus Timing Examples........................................................................................... 17-13
17.4.6 Burst Cycles ................................................................................................................. 17-24
17.4.7 Misaligned Operands ................................................................................................... 17-30
17.4.8 Bus Errors .................................................................................................................... 17-30
18.1 Introduction .................................................................................................................................. 18-1
xiv
Contents
Title
n
Status Monitoring ................................................................................. 16-35
Chapter 17
FlexBus
Chapter 18
SDRAM Controller (SDRAMC)
MCF5329 Reference Manual, Rev 3
Page
Number
Freescale Semiconductor