Freescale Semiconductor MCF5329 Reference Manual page 25

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32.2.2 I C Frequency Divider Register (I2FDR)...................................................................... 32-3
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32.2.3 I C Control Register (I2CR) .......................................................................................... 32-4
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32.2.4 I C Status Register (I2SR)............................................................................................. 32-5
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32.2.5 I C Data I/O Register (I2DR) ........................................................................................ 32-6
32.3 Functional Description ................................................................................................................. 32-7
32.3.1 START Signal................................................................................................................ 32-7
32.3.2 Slave Address Transmission .......................................................................................... 32-8
32.3.3 Data Transfer ................................................................................................................. 32-8
32.3.4 Acknowledge ................................................................................................................. 32-9
32.3.5 STOP Signal .................................................................................................................. 32-9
32.3.6 Repeated START ........................................................................................................... 32-9
32.3.7 Clock Synchronization and Arbitration ....................................................................... 32-11
32.3.8 Handshaking and Clock Stretching.............................................................................. 32-12
32.4 Initialization/Application Information ....................................................................................... 32-12
32.4.1 Initialization Sequence................................................................................................. 32-12
32.4.2 Generation of START.................................................................................................. 32-12
32.4.3 Post-Transfer Software Response ................................................................................ 32-13
32.4.4 Generation of STOP..................................................................................................... 32-13
32.4.5 Generation of Repeated START.................................................................................. 32-14
32.4.6 Slave Mode .................................................................................................................. 32-14
32.4.7 Arbitration Lost............................................................................................................ 32-14
Message Digest Hardware Accelerator (MDHA)
33.1 Introduction .................................................................................................................................. 33-1
33.1.1 Overview........................................................................................................................ 33-1
33.1.2 Features .......................................................................................................................... 33-1
33.1.3 Modes of Operation ....................................................................................................... 33-2
33.2 Memory Map/Register Definition................................................................................................ 33-3
33.2.1 MDHA Mode Register (MDMR) .................................................................................. 33-3
33.2.2 MDHA Control Register (MDCR) ................................................................................ 33-6
33.2.3 MDHA Command Register (MDCMR) ........................................................................ 33-7
33.2.4 MDHA Status Register (MDSR) ................................................................................... 33-8
33.2.5 MDHA Interrupt Status & Mask Registers (MDISR and MDIMR) ............................. 33-9
33.2.6 MDHA Data Size Register (MDDSR)......................................................................... 33-11
33.2.7 MDHA Input FIFO (MDIN)........................................................................................ 33-11
33.2.8 MDHA Message Digest Registers 0 (MDx0).............................................................. 33-11
33.2.9 MDHA Message Data Size Register (MDMDS)......................................................... 33-12
33.2.10 MDHA Message Digest Registers 1 (MDx1).............................................................. 33-12
Freescale Semiconductor
Contents
Title
Chapter 33
MCF5329 Reference Manual, Rev 3
Page
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