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FlexCAN
23.3.8
Interrupt Flag Register (IFLAG)
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAG bit and, if the corresponding IMASK bit is set, generates an interrupt.
The interrupt flag is cleared by writing a 1, while writing 0 has no effect.
Address: 0xFC02_0030 (IFLAG)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved, must be cleared.
15–0
Buffer interrupt flag. Indicates a successful transmission/reception for the corresponding message buffer. If the
BUFnI
corresponding IMASK bit is set, an interrupt request is generated. The user must write a 1 to clear an interrupt flag;
writing 0 has no effect.
0 No such occurrence.
1 The corresponding buffer has successfully completed transmission or reception.
23.3.9
Message Buffer Structure
The message buffer memory map starts at an offset of 0x80 from the FlexCAN's base address
(0xFC02_0000). The 256-byte message buffer space is fully used by the16 message buffer structures.
Each message buffer consists of a control and status field that configures the message buffer, an identifier
field for frame identification, and up to 8 bytes of data.
23-16
Figure 23-11. FlexCAN Interrupt Flags Register (IFLAG)
Table 23-10. IFLAG Field Descriptions
MCF5329 Reference Manual, Rev 3
8
BUFnI
w1c
Description
Access: User read/write
7
6
5
4
3
2
1
0
Freescale Semiconductor
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