Paragraph
Number
20.1.1
Block Diagram ............................................................................................................... 20-2
20.1.2
Overview........................................................................................................................ 20-2
20.1.3
Features .......................................................................................................................... 20-2
20.1.4
Modes of Operation ....................................................................................................... 20-3
20.2.1
20.4 Functional Description ................................................................................................................. 20-6
21.1 Introduction .................................................................................................................................. 21-1
21.1.1
Overview........................................................................................................................ 21-1
21.1.2
Block Diagram ............................................................................................................... 21-2
21.1.3
Features .......................................................................................................................... 21-3
21.1.4
Modes of Operation ....................................................................................................... 21-4
21.2.1
21.3.1
21.3.2
Capability Registers ..................................................................................................... 21-13
21.3.3
Operational Registers................................................................................................... 21-16
21.4 Functional Description ............................................................................................................... 21-45
21.4.1
System Interface .......................................................................................................... 21-45
21.4.2
DMA Engine................................................................................................................ 21-45
21.4.3
FIFO RAM Controller ................................................................................................. 21-45
21.4.4
Physical Layer (PHY) Interface................................................................................... 21-45
21.5 Initialization/Application Information ....................................................................................... 21-46
21.5.1
Host Operation ............................................................................................................. 21-46
21.5.2
Device Data Structures ................................................................................................ 21-47
21.5.3
Device Operation ......................................................................................................... 21-54
21.5.4
Servicing Interrupts...................................................................................................... 21-72
21.5.5
22.1 Introduction .................................................................................................................................. 22-1
22.1.1
Block Diagram ............................................................................................................... 22-1
Freescale Semiconductor
Contents
Title
Chapter 21
Chapter 22
Liquid Crystal Display Controller (LCDC)
MCF5329 Reference Manual, Rev 3
Page
Number
xvii