Freescale Semiconductor MCF5329 Reference Manual page 273

Field
31–0 Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an
INT interrupt condition can generate an interrupt. At every system clock, the IPRLn samples the signal generated by the
interrupting source. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding
IMRLn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
14.2.2 Interrupt Mask Register (IMRHn, IMRLn)
The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt to allow
the request to be disabled (1 equals disable the request, 0 equals enable the request). The IMRL register is
used for masking interrupt sources 0 to 31, while the IMRH register is used for masking interrupts 32 to
63. The IMRn is set to all ones by reset, disabling all interrupt requests. The IMRn can be read and written.
A spurious interrupt may occur if an interrupt source is being masked in the
interrupt controller mask register (IMR) or a module's interrupt mask
register while the interrupt mask in the status register (SR[I]) is set to a value
lower than the interrupt's level. This is because by the time the status
register acknowledges this interrupt, the interrupt has been masked. A
spurious interrupt is generated because the CPU cannot determine the
interrupt source. To avoid this situation for interrupts sources with levels
1-6, first write a higher level interrupt mask to the status register, before
setting the mask in the IMR or the module's interrupt mask register. After
the mask is set, return the interrupt mask in the status register to its previous
value. Because level 7 interrupts cannot be disabled in the status register
prior to masking, use of the IMR or module interrupt mask registers to
disable level 7 interrupts is not recommended.
Address 0xFC04_8008 (IMRH0)
0xFC04_C008 (IMRH1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Freescale Semiconductor
Table 14-4. IPRLn Field Descriptions
Description
NOTE
Figure 14-3. Interrupt Mask Register High (IMRHn)
MCF5329 Reference Manual, Rev 3
INT_MASK
Interrupt Controller Modules
Access: User read/write
8 7 6 5 4 3 2 1 0
14-5