Freescale Semiconductor MCF5329 Reference Manual page 378

SDRAM Controller (SDRAMC)
Field
29 DDR mode select.
DDR_MODE 0 SDR mode
1 DDR mode
28 Refresh enable.
REF_EN 0 Automatic refresh disabled
1 Automatic refresh enabled
27–26 Reserved, must be cleared.
25–24 Controls the use of internal address bits A[27:24] as row or column bits on the SD_A bus. See
ADDR_MUX Table 18-5.
23 Reserved, must be cleared.
22 Drive rule selection.
OE_RULE 0 Tri-state except to write. SD_D and SD_DQS are only driven when necessary to perform a write command.
1 Drive except to read. SD_D and SD_DQS are only tristated when necessary to perform a read command.
When not being driven for a write cycle, SD_D hold the most recent value and SD_DQS are driven low. This
mode is intended for minimal applications only, to prevent floating signals and allow unterminated board
traces. However, terminated wiring is always recommended over unterminated.
21–16 The average periodic interval at which the controller generates refresh commands to memory; measured in
increments of 64 × SD_CLK period.
REF_CNT
REF_CNT = (t
If the SDRAM data sheet does not define t
15–14 Reserved, must be cleared.
13 Memory data port size.
MEM_PS 0 32-bit data bus
1 16-bit data bus
12 Reserved, must be cleared.
11–10 DQS output enable. Each DQS_OE bit is a master enable for the corresponding SD_DQSn signal. DQS_OE[1]
DQS_OE (SDCR[11]) enables SD_DQS3 and DQS_OE[0] (SDCR[10]) enables SD_DQS2.
0 SD_DQSn can never drive. Use this value in SDR mode or in DDR mode with a single DQS memory. Some
32-bit DDR devices have only a single DQS pin. Enable one of the SD_DQSn signals and disable the other.
Then, short both pins external to the device.
1 SD_DQSn can drive as necessary, depending on commands and SDCR[OE_RULE] setting. DDR only.
9–3 Reserved, must be cleared.
2 Initiate refresh command. Used to force a software-initiated refresh command. This bit is write-only, reads return
IREF zero.
0 Do not generate a refresh command.
1 Generate a refresh command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be set
before attempting to generate a software refresh command.
Note: A software requested refresh is completely independent of the periodic refresh interval counter. Software
refresh is only possible when MODE_EN is set.
18-16
Table 18-8. SDCR Field Descriptions (continued)
× 64)) - 1, rounded down to the next integer value.
/ (t
REFI CK
REFI
MCF5329 Reference Manual, Rev 3
Description
, it can be calculated by t
REFI
Table 18-4, and
= t / #rows.
REF
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