Misaligned Operands; Bus Errors - Freescale Semiconductor MCF5329 Reference Manual

FlexBus
17.4.7

Misaligned Operands

Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned.
• Byte operand is properly aligned at any address
• Word operand is misaligned at an odd address
• Longword is misaligned at any address not a multiple of four
Although the processor enforces no alignment restrictions for data operands (including program counter
(PC) relative data addressing), misaligned operands require additional bus cycles.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch
a misaligned instruction word causes an address-error exception.
The processor core converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.
Example 17-1 shows the transfer of a longword operand from a byte address to a 32-bit port. First, a byte
transfers at an offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When
the processor starts the second cycle, a word transfers with a byte offset of 0x2. The next two bytes are
transferred in this cycle. In the third cycle, byte 3 transfers. The byte offset is now 0x0, the port supplies
the final byte, and the operation completes.
Transfer 1
Transfer 2
Transfer 3
Example 17-1. A Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the
cache. The example in Example 17-2
word-sized and the transfer takes only two bus cycles.
Transfer 1
Transfer 2
17.4.8

Bus Errors

The ColdFire device has no bus monitor. If the auto-acknowledge feature is not enabled for the address
that generates the error, the bus cycle can be terminated by asserting FB_TA or by using the software
watchdog timer. If the processor must manage a bus error differently, asserting an interrupt to the core
along with FB_TA when the bus error occurs can invoke an interrupt handler.
17-30
31 24 23
–– Byte 0
–– ––
––
Byte 3
differs from the one in
31 24 23
–– ––
Byte 0 ––
Example 17-2. A Misaligned Word Transfer (32-Bit Port)
MCF5329 Reference Manual, Rev 3
16 15 8 7
–– ––
Byte 1 Byte 2
–– ––
Example 17-1
16 15 8 7
–– Byte 0
–– —
0 FB_A[2:0]
001
010
100
because the operand is
0 FB_A[2:0]
001
100
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