Freescale Semiconductor MCF5329 Reference Manual page 519

– No more than 4 periodic transactions (interrupt/isochronous) can be scheduled through the
embedded TT per frame.
— Complete-split transaction searching.
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 ms) or else
undefined behavior may result.
21.5.5.2 Device Operation
The co-existence of a device operational controller within the USB OTG module has little effect on EHCI
compatibility for host operation. However, given that the USB OTG controller initializes in neither host
nor device mode, the USBMODE register must be programmed for host operation before the EHCI host
controller driver can begin EHCI host operations.
21.5.5.3 Non-Zero Fields in the Register File
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
use in device mode. Adhere to these steps:
• Write operations to all EHCI reserved fields (some of which are device fields in the USB OTG
module) in the operation registers should always be written to zero. This is an EHCI requirement
of the device controller driver that must be adhered to.
• Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the USB OTG module registers).
21.5.5.4 SOF Interrupt
The SOF interrupt is a free running 125 µs interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. The free running interrupt is
shared with the device mode start-of-frame interrupt. See
(USBSTS)," and Section 21.3.3.3, "USB Interrupt Enable Register (USBINTR),"
21.5.5.5 Embedded Design
This is an embedded USB host controller as defined by the EHCI specification; therefore, it does not
implement the PCI configuration registers.
21.5.5.5.1 Frame Adjust Register
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the frame adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µs using the transceiver clock as
a reference clock or a 60 Mhz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces.
Freescale Semiconductor
NOTE
Section 21.3.3.2, "USB Status Register
MCF5329 Reference Manual, Rev 3
Universal Serial Bus Interface – On-The-Go Module
for more information.
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