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19.2.3
Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),
and multicast hash match. Address recognition options are discussed in detail in
Address Recognition."
19.2.4
Internal Loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 19.5.14, "MII Internal and External Loopback."
19.3
External Signal Description
Table 19-1
describes the various FEC signals, as well as indicating which signals work in available modes.
Signal Name
FEC_COL
X
X
FEC_CRS
X
— When asserted, indicates that transmit or receive medium is not idle.
FEC_MDC
X
— Output clock which provides a timing reference to the PHY for data transfers on the FEC_MDIO
FEC_MDIO
X
— Transfers control information between the external PHY and the media-access controller. Data
FEC_RXCLK
X
X
FEC_RXDV
X
X
FEC_RXD0
X
X
FEC_RXD1
X
— This pin contains the Ethernet input data transferred from the PHY to the media access
FEC_RXD[3:2]
X
— These pins contain the Ethernet input data transferred from the PHY to the media access
FEC_RXER
X
— When asserted with FEC_RXDV, indicates that the PHY has detected an error in the current
FEC_TXCLK
X
X
FEC_TXD0
X
X
FEC_TXD1
X
— This pin contains the serial output Ethernet data and is valid only during assertion of
FEC_TXD[3:2]
X
— These pins contain the serial output Ethernet data and are valid only during assertion of
Freescale Semiconductor
Table 19-1. FEC Signal Descriptions
Asserted upon detection of a collision and remains asserted while the collision persists. This
signal is not defined for full-duplex mode.
signal.
is synchronous to FEC_MDC. This signal is an input after reset. When the FEC is operated in
10Mbps 7-wire interface mode, this signal should be connected to VSS.
Provides a timing reference for FEC_RXDV, FEC_RXD[3:0], and FEC_RXER.
Asserting the FEC_RXDV input indicates that the PHY has valid nibbles present on the MII.
FEC_RXDV should remain asserted from the first recovered nibble of the frame through to the
last nibble. Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF.
This pin contains the Ethernet input data transferred from the PHY to the media-access
controller when FEC_RXDV is asserted.
controller when FEC_RXDV is asserted.
controller when FEC_RXDV is asserted.
frame. When FEC_RXDV is not asserted FEC_RXER has no effect.
Input clock which provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and FEC_TXER.
The serial output Ethernet data and is only valid during the assertion of FEC_TXEN.
FEC_TXEN.
FEC_TXEN.
MCF5329 Reference Manual, Rev 3
Fast Ethernet Controller (FEC)
Section 19.5.9, "Ethernet
Description
19-5
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