Freescale Semiconductor MCF5329 Reference Manual page 608

Synchronous Serial Interface (SSI)
Field
7 Master clock enable. Allows the SSI to output the master clock at the SSI_MCLK port, if network mode and transmit
MCE internal clock mode are set. The DIV2, PSR, and PM bits determine the relationship between the bit clock
(SSI_BCLK) and SSI_MCLK. In I
0 Master clock not output on the SSI_MCLK pin
1 Master clock output on the SSI_MCLK pin
2
6–5 I S mode select. Selects normal, I
2
I2S description of I S mode.
00 Normal mode
2
01 I S master mode
2
10 I S slave mode
11 Normal mode
4 Synchronous mode enable. In synchronous mode, transmit and receive sections of SSI share a common clock port
SYN (SSI_BCLK) and frame sync port (SSI_FS).
0 Reserved.
1 Synchronous mode selected.
3 Network mode enable.
NET 0 Network mode not selected
1 Network mode selected
2 Receiver enable. When this bit is set, data reception starts with the arrival of the next frame sync. If data is received
RE when this bit is cleared, data reception continues with the end of the current frame and then stops. If this bit is set
again before the second to last bit of the last time slot in the current frame, reception continues without interruption.
0 Receiver disabled
1 Receiver enabled
1 Transmitter. Enables the transfer of the contents of the SSI_TX registers to the TXSR, and also enables the internal
TE transmit clock. The transmit section is enabled when this bit is set and a frame boundary is detected.
When this bit is cleared, the transmitter continues to send data until the end of the current frame and then stops.
Data can be written to the SSI_TX registers with the TE bit cleared (the corresponding TDE bit is cleared). If the TE
bit is cleared and set again before the second to last bit of the last time slot in the current frame, data transmission
continues without interruption.
The normal transmit enable sequence is to:
1. Write data to the SSI_TX register(s)
2. Set the TE bit
The normal transmit disable sequence is to:
1. Wait for TDE to set
2. Clear the TE and TIE bits
In gated clock mode, clearing the TE bit results in the clock stopping after the data currently in TXSR has shifted out.
When the TE bit is set, the clock starts immediately in internal gated clock mode.
0 Transmitter disabled
1 Transmitter enabled
0 SSI enable. When disabled, all SSI status bits are reset to the same state produced by the power-on reset, all control
SSI_EN bits are unaffected, and the contents of Tx and Rx FIFOs are cleared. When SSI is disabled, all internal clocks are
disabled (except the register access clock).
0 SSI module is disabled
1 SSI module is enabled
24-14
Table 24-7. SSI_CR Field Descriptions (continued)
Description
2
S master mode, this bit is used to output the oversampling clock on SSI_MCLK.
2 2
S master, or I S slave mode. Refer to
MCF5329 Reference Manual, Rev 3
Section 24.4.1.4, "I2S Mode,"
Freescale Semiconductor
for a detailed