Freescale Semiconductor MCF5329 Reference Manual page 850

Debug Module
Result Data: Control register contents are returned as a longword, most-significant word first.
The implemented portion of registers smaller than 32 bits is guaranteed correct;
other bits are undefined.
Rc encoding: See Table
0x002
0x004
0x005
0x009
0x(0,1)80 – 0x(0,1)87
0x(0,1)88 – 0x(0,1)8F
0x800
0x801
0x804
0x805
0x806
0x807
0x808
0x809
0x80A
0x80B
0x80E
0x80F
0xC05
1
If an RGPIO module is available on this device.
36.4.1.5.11 BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)
The ColdFire core supports two unique stack pointer (A7) registers: the supervisor stack pointer (SSP) and
the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit
registers does not uniquely identify one as the SSP and the other as the USP. Rather, the hardware uses one
32-bit register as the currently-active A7; the other is named the OTHER_A7. Therefore, the contents of
the two hardware registers is a function of the operating mode of the processor:
if SR[S] = 1
then A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
else A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
36-34
36-21.
Table 36-21. Control Register Map
Rc
RGPIO Base Address Register (RGPIOBAR)
Data Registers 0–7 (0 = load, 1 = store)
Address Registers 0–7 (0 = load, 1 = store)
MAC Accumulator 0,1 Extension Bytes (ACCEXT01)
MAC Accumulator 2,3 Extension Bytes (ACCEXT23)
RAM Base Address Register (RAMBAR)
MCF5329 Reference Manual, Rev 3
Register Definition
Cache Control Register (CACR)
Access Control Register (ACR0)
Access Control Register (ACR1)
(A7 is user stack pointer)
Other Stack Pointer (OTHER_A7)
Vector Base Register (VBR)
MAC Status Register (MACSR)
MAC Mask Register (MASK)
MAC Accumulator 0 (ACC0)
MAC Accumulator 1 (ACC1)
MAC Accumulator 2 (ACC2)
MAC Accumulator 3 (ACC3)
Status Register (SR)
Program Register (PC)
1
Freescale Semiconductor