Freescale Semiconductor MCF5329 Reference Manual page 908

Revision History
Table B-2. MCF5329RM Rev 1 to Rev. 2 Changes (continued)
Chapter
Core Table 3-1/Page 3-5: Change PC's Reset Value entry to "Contents of Location 0x0000_0004" and Written with
MOVEC entry to "No".
Table 3-1/Page 3-5: Change OTHER_A7's Reset Value entry to "Contents of Location 0x0000_0000".
Figure 3-5/Page 3-7: Change "Access: User read-only" to "Access: read/write".
Change CCR[4:0] to read/write.
Table 3-2/Page 3-8: Remove last sentence in C bit field description.
Figure 3-8/Page 3-9: Change SR[4:0] to read/write.
Section 3.4/Page 3-11: Change last bullet to "Use of separate system stack pointers for user and supervisor
modes"
Section 3.4/Page 3-11: Change last sentence in step #2 to "The IACK cycle is mapped to special locations within
the interrupt controller's address space with the interrupt level encoded in the address."
EMAC Changed all mov instructions to move.
Figure 4-4/Page 4-5: Change MACSR[3:0] to R/W
Figure 4-5/Page 4-10: Change upper 16 bits of the MASK register to read-only, with a read and reset value of 1
Equation 4-3/Page 4-13: Add minus sign to the exponent so that it is "–(i + 1 – N)".
Cache Rearranged sections for consistency.
Table 5-2/Page 5-4: Change reset value of ACR0, ACR1 to "See Section" because some of the bits are defined
after reset.
Section 5.3.2/Page 5-6: Add the following note:
Section 5.4.6/Page 5-14: Change first sentence from "Ways 0 and 1 of the data cache can be locked by setting
CACR[DHLCK]; likewise, ways 0 and 1 of the instruction cache can be locked by setting CACR[IHLCK]." to
""Ways 0 and 1 of the cache can be locked by setting CACR[HLCK]."
Figure 5-8/Page 5-15: Change sentence near top of figure from "B) CACR[DHLCK] is set, locking ways 0 and
1." to "B) CACR[HLCK] is set, locking ways 0 and 1."
PLL Remove "the user must wait for the PLL to lock before continuing with code execution." from third paragraph in
the Limp Mode section.
Power Table 8-9/Page 8-8: Added the following note to the LPCR[FWKUP] (fast wake-up) bit description:
Note: Setting this bit is potentially dangerous and unreliable. The system may behave unpredictably when using
an unlocked clock, because the clock frequency could overshoot the maximum frequency of the device.
Removed last sentence in first paragraph of Limp Mode section regarding switching from limp to normal mode.
CCM Section 9.3.5/Page 9-6: The CDR[SSIDIV] field is a 6-bit field. Expand the field in the figure and bit description
table from bits 3–0 to bits 5–0
Table 9-5/Page 9-5: Replace instances of "HCLK" in the LCDCHEN bit description to "internal clock".
SCM Section 11.2.8/Page 11-10: Combine all BCR[7:0] fields into a single slave burst enable field, SBE. The only
valid values for this field are 0x00 and 0xFF. All other values are reserved.
Added last sentence to first paragraph in PACRx section, "At reset the SCM (PACR0) does not allow access
from untrusted masters, while the other peripherals do."
B-6
Peripheral space (0xE000_0000-0xFFFF_FFFF) should not be cached.
The combination of the CACR defaults and the two ACRn registers must
define the non-cacheable attribute for this address space.
MCF5329 Reference Manual, Rev 3
Description
NOTE
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