Freescale Semiconductor MCF5329 Reference Manual page 741

framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error
and break flags in the USRn at the received character boundary. They are valid only if USRn[RXRDY] is
set.
If a break condition is detected (UnRXD is low for the entire character including the stop bit), a character
of all 0s loads into the receiver holding register and USRn[RB,RXRDY] are set. UnRXD must return to a
high condition for at least one-half bit time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break persists through the
next character time. If the break begins in the middle of a character, receiver places the damaged character
in the Rx FIFO and sets the corresponding USRn error bits and USRn[RXRDY]. Then, if the break lasts
until the next character time, receiver places an all-zero character into the Rx FIFO and sets
USRn[RB,RXRDY].
Figure 31-20 shows receiver functional timing.
UnRXD
Receiver
Enabled
USRn[RXRDY]
USRn[FFULL]
internal
module
select
Overrun
USRn[OE]
Manually asserted first time,
1
UnRTS
automatically negated if overrun occurs
UOP0[RTS] = 1
1
UMR2n[RXRTS] = 1
31.4.2.3 FIFO
The FIFO is used in the UART's receive buffer logic. The FIFO consists of three receiver holding registers.
The receive buffer consists of the FIFO and a receiver shift register connected to the UnRXD (see
Figure 31-18). Data is assembled in the receiver shift register and loaded into the top empty receiver
holding register position of the FIFO. Therefore, data flowing from the receiver to the CPU is
quadruple-buffered.
In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break
(RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By
Freescale Semiconductor
C1 C2 C3
Status
Data
(C1)
Figure 31-20. Receiver Timing Diagram
MCF5329 Reference Manual, Rev 3
C4 C5 C6
Status
Data
C5 is
(C2)
lost
Automatically asserted
when ready to receive
UART Modules
C8
C7
C6, C7, and C8 is lost
Status Status
Data Data
(C3) (C4)
Reset by
command
31-21