Freescale Semiconductor MCF5329 Reference Manual page 851

The BDM programming model supports reads and writes to A7 and OTHER_A7 directly. It is the
responsibility of the external development system to determine the mapping of A7 and OTHER_A7 to the
two program-visible definitions (supervisor and user stack pointers), based on the SR[S] bit.
36.4.1.5.12 BDM Accesses of the EMAC Registers
The presence of rounding logic in the output datapath of the EMAC requires special care for
BDM-initiated reads and writes of its programming model. In particular, any result rounding modes must
be disabled during the read/write process so the exact bit-wise EMAC register contents are accessed.
For example, a BDM read of an accumulator (ACCx) must be preceded by two commands accessing the
MAC status register, as shown in the following sequence:
BdmReadACCx (
rcreg macsr;
wcreg #0,macsr;
rcreg ACCx;
wcreg #saved_data,macsr;// restore the original macsr
)
Likewise, to write an accumulator register, the following BDM sequence is needed:
BdmWriteACCx (
rcreg macsr;
wcreg #0,macsr;
wcreg #data,ACCx;
wcreg #saved_data,macsr;// restore the original macsr
)
Additionally, writes to the accumulator extension registers must be performed after the corresponding
accumulators are updated because a write to any accumulator alters the corresponding extension register
contents.
For more information on saving and restoring the complete EMAC programming model, see
Section 4.3.1.2, "Saving and Restoring the EMAC Programming Model."
36.4.1.5.13 Write Control Register (
The operand (longword) data is written to the specified control register. The write alters all 32 register bits.
See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7
stack pointers and the EMAC programming model.
Command/Result Formats:
15 14
Command
Result
Freescale Semiconductor
// read current macsr contents and
// disable all rounding modes
// read the desired accumulator
// read current macsr contents and
// disable all rounding modes
// write the desired accumulator
WCREG
13 12 11 10
0x2 0x8
0x0 0x0
0x0
Figure 36-37.
WCREG
MCF5329 Reference Manual, Rev 3
)
9 8 7 6 5
0x8
0x0
Rc
D[31:16]
D[15:0]
Command/Result Formats
Debug Module
save
save
4 3 2 1 0
0x0
0x0
36-35