Freescale Semiconductor MCF5329 Reference Manual page 28

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Number
37.1 Introduction .................................................................................................................................. 37-1
37.1.1 Block Diagram ............................................................................................................... 37-1
37.1.2 Features .......................................................................................................................... 37-2
37.1.3 Modes of Operation ....................................................................................................... 37-2
37.2 External Signal Description ......................................................................................................... 37-2
37.2.1 JTAG Enable (JTAG_EN)............................................................................................. 37-2
37.2.2 Test Clock Input (TCLK) .............................................................................................. 37-3
37.2.3 Test Mode Select/Breakpoint (TMS/BKPT) ................................................................. 37-3
37.2.4 Test Data Input/Development Serial Input (TDI/DSI) .................................................. 37-3
37.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) ............................................... 37-4
37.2.6 Test Data Output/Development Serial Output (TDO/DSO).......................................... 37-4
37.3 Memory Map/Register Definition................................................................................................ 37-4
37.3.1 Instruction Shift Register (IR) ....................................................................................... 37-4
37.3.2 IDCODE Register .......................................................................................................... 37-5
37.3.3 Bypass Register.............................................................................................................. 37-5
37.3.4 TEST_CTRL Register ................................................................................................... 37-5
37.3.5 Boundary Scan Register................................................................................................. 37-6
37.4 Functional Description ................................................................................................................. 37-6
37.4.1 JTAG Module ................................................................................................................ 37-6
37.4.2 TAP Controller .............................................................................................................. 37-6
37.4.3 JTAG Instructions.......................................................................................................... 37-7
37.5 Initialization/Application Information ....................................................................................... 37-10
37.5.1 Restrictions .................................................................................................................. 37-10
37.5.2 Nonscan Chain Operation ............................................................................................ 37-10
A.1 Register Memory Map .................................................................................................... A-1
B.1 Changes Between Rev. 2 and Rev. 3 ...............................................................................B-1
B.2 Changes Between Rev. 1 and Rev. 2 ...............................................................................B-5
B.3 Changes Between Rev. 0.1 and Rev. 1 ..........................................................................B-12
B.4 Changes Between Rev. 0 and Rev. 0.1 ..........................................................................B-17
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Contents
Title
Chapter 37
IEEE 1149.1 Test Access Port (JTAG)
Appendix A
Register Memory Map Quick Reference
Appendix B
Revision History
MCF5329 Reference Manual, Rev 3
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Number
Freescale Semiconductor