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Random Number Generator (RNG)
See Appendix D of the NIST Special Publication 800-90 "Recommendation
for Random Number Generation Using Deterministic Random Bit
Generators" for more information:
34.2
Memory Map/Register Definition
Table 34-1
shows the address map for the RNG module. Detailed register descriptions are found in the
following section.
Address
0xEC08_8000 RNG Control Register (RNGCR)
0xEC08_8004 RNG Status Register (RNGSR)
0xEC08_8008 RNG Entropy Register (RNGER)
0xEC08_800C RNG Output FIFO (RNGOUT)
34.2.1
RNG Control Register (RNGCR)
Immediately following reset, the RNG begins generating entropy (random data) in its internal shift
registers. Random data is not pushed to the output FIFO until after the RNGCR[GO] bit is set. After this,
a random 32-bit word is pushed to the FIFO every 256 cycles. If the FIFO is full, no push occurs. The FIFO
is kept as close to full as possible.
Address: 0xEC08_8000 (RNGCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–5
Reserved, must be cleared.
4
Sleep mode. The RNGA can be placed in low power mode by setting this bit. When this bit is set, the oscillators are
SLM
disabled.Clearing this bit causes the RNGA to exit sleep mode. The FIFO is not pushed while the RNGA is in sleep
mode.
0 RNGA is not in sleep mode.
1 RNGA is in sleep mode.
3
Clear interrupt. Writing a 1 to this bit clears the error interrupt and RNGSR[EI]. This bit is self-clearing,
CI
0 Do not clear error interrupt.
1 Clear error interrupt.
34-2
NOTE
http://csrc.nist.gov
Table 34-1. RNG Block Memory Map
Register
Figure 34-1. RNG Control Register (RNGCR)
Table 34-2. RNGCR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Width
Access Reset Value
(bits)
32
R/W
0x0000_0000
32
R
0x0010_0000
32
W
0x0000_0000
32
R
0x0000_0000
Access: User read/write
9
8
7
6
5
SLM
Freescale Semiconductor
Section/Page
34.2.1/34-2
34.2.2/34-3
34.2.3/34-4
34.2.4/34-4
4
3
2
1
0
0
IM HA GO
CI
0
0
0
0
0
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