Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

Interrupt Controller Modules
space within the interrupt controller. The fetched data provides an index into the exception vector table
that contains 256 addresses, each pointing to the beginning of a specific exception service routine. In
particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt service routines.
The first 64 exception vectors are reserved for the processor to manage reset, error conditions (access,
address), arithmetic faults, system calls, etc. After the interrupt vector number has been retrieved, the
processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2
longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program
counter value of the instruction that was interrupted (see
Definition," for more information on the stack frame format). After the exception stack frame is stored in
memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number
as the offset, and then jumps to that address to begin execution of the service routine. After the status
register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being
acknowledged, effectively masking that level and all lower values while in the service routine.
The processing of the interrupt acknowledge cycle is fundamentally different than previous 68K/ColdFire
cores. In this approach, all IACK cycles are directly managed by the interrupt controller, so the requesting
peripheral device is not accessed during the IACK. As a result, the interrupt request must be explicitly
cleared in the peripheral during the interrupt service routine. For more information, see
"Interrupt Vector Determination."
ColdFire processors guarantee that the first instruction of the service routine is executed before sampling
for interrupts is resumed. By making this initial instruction a load of the SR, interrupts can be safely
disabled, if required.
For more information on exception processing, see the ColdFire Programmer's Reference Manual at
http://www.freescale.com/coldfire.
14.2

Memory Map/Register Definition

The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In
the following discussion, there are a number of program-visible registers greater than 32 bits in size. For
these control fields, the physical register is partitioned into two 32-bit values: a register high (the upper
longword) and a register low (the lower longword). The nomenclature <reg_name>H and <reg_name>L
is used to reference these values.
The registers and their locations are defined in
are listed below.
Interrupt Controller Number
Global IACK Registers Space
1
This address space only contains the global SWIACK and global L1ACK-L7IACK registers. See
Section 14.2.10, "Software and Level 1 – 7 IACK Registers (SWIACKn, L1IACKn –
information
14-2
Table
Table 14-1. Interrupt Controller Base Addresses
INTC0
INTC1
1
MCF5329 Reference Manual, Rev 3
Section 3.3.3.1, "Exception Stack Frame
14-2. The base addresses for the interrupt controllers
Base Address
0xFC04_8000
0xFC04_C000
0xFC05_4000
Section 14.3.1.3,
L7IACKn)" for more
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