Freescale Semiconductor MCF5329 Reference Manual page 672

Pulse-Width Modulation (PWM) Module
and/or period values to be latched. In addition, because the counter is readable, it is possible to know where
the count is with respect to the duty value, and software can be used to make adjustments. When forcing
a new period or duty into effect immediately, an irregular PWM cycle can occur.
Depending on the polarity bit, the duty registers contain the count of the high time or the low time.
26.3.2.4 PWM Timer Counters
Each channel has a dedicated 8-bit up/down counter that runs at the rate of the selected clock source (see
Figure 26-14 for the available clock sources and rates). The counter compares to two registers, a duty
register and a period register, as shown in
the output flip-flop changes state, causing the PWM waveform to also change state. A match between the
PWM counter and the period register behaves differently depending on what output mode is selected as
shown in Figure 26-15 and described in
"Center-Aligned Outputs."
Each channel counter can be read at anytime without affecting the count or the operation of the PWM
channel.
Any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up,
the immediate load of duty and period registers with values from the buffers, and the output to change
according to the polarity bit. When the channel is disabled (PWMEn = 0), the counter stops. When a
channel becomes enabled (PWMEn = 1), the associated PWM counter continues from the count in the
PWMCNTn register. This allows the waveform to continue where it left off when the channel is
re-enabled. When the channel is disabled, writing 0 to the period register causes the counter to reset on the
next selected clock.
If the user wants to start a new clean PWM waveform without any history
from the old waveform, the user must write to channel counter
(PWMCNTn) prior to enabling the PWM channel (PWMEn = 1).
Generally, writes to the counter are done prior to enabling a channel to start from a known state. However,
writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to
writing the counter when the channel is disabled, except that the new period is started immediately with
the output set according to the polarity bit. Writing to the counter while the channel is enabled can cause
an irregular PWM cycle to occur.
The counter is cleared at the end of the effective period (see
Section 26.3.2.6, "Center-Aligned Outputs"
Counter Clears (0x00)
When PWMCNTn register written to any
value
Effective period ends
26-16
Figure 26-15. When the PWM counter matches the duty register,
Section 26.3.2.5, "Left-Aligned Outputs"
NOTE
for more details).
Table 26-14. PWM Timer Counter Conditions
Counter Counts
When PWM channel is enabled
(PWMEn = 1). Counts from last value
in PWMCNTn.
MCF5329 Reference Manual, Rev 3
and
Section 26.3.2.5, "Left-Aligned Outputs"
Counter Stops
When PWM channel is disabled
(PWMEn = 0)
Section 26.3.2.6,
and
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