External Reset - Freescale Semiconductor MCF5329 Reference Manual

Clock Module
7.3.5.2

External Reset

When RESET is asserted, the PLL input clock is output to the device and the PLL does not begin acquiring
lock until RESET is negated. The MISCCR[PLLLOCK] bit is cleared and remains cleared while the PLL
is acquiring lock. This bit is set after the PLL lock period of 1 ms has passed.
When running in an unlocked state, the clocks generated by the PLL are not
guaranteed to be stable and may exceed the maximum specified frequency
of the device.
7-12
CAUTION
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor