Freescale Semiconductor MCF5329 Reference Manual page 60

Signal Descriptions
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO
SSI_FS PSSI2
2
SSI_RXD PSSI1
2
SSI_TXD PSSI0
2
SSI_RXD PSSI1
2
SSI_TXD PSSI0
2
I2C_SCL PFECI2C1
2
I2C_SDA PFECI2C0
2
I2C_SCL PFECI2C1
2
I2C_SDA PFECI2C0
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
QSPI_CS2 PQSPI5
QSPI_CS1 PQSPI4
QSPI_CS0 PQSPI3
QSPI_CLK PQSPI2
QSPI_DIN PQSPI1
QSPI_DOUT PQSPI0
U1CTS PUARTL7
U1RTS PUARTL6
U1TXD PUARTL5
U1RXD PUARTL4
U0CTS PUARTL3
U0RTS PUARTL2
U0TXD PUARTL1
U0RXD PUARTL0
Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.
2-6
Alternate 1 Alternate 2
U2RTS PWM5
U2RXD CANRX
U2TXD CANTX
U2RXD —
U2TXD —
2
I C
CANTX U2TXD
CANRX U2RXD
— U2TXD
— U2RXD
DMA
QSPI
U2RTS —
PWM7 USBOTG_
PU_EN
PWM5 —
2
I2C_SCL —
U2CTS —
I2C_SDA —
UARTs
SSI_BCLK —
SSI_FS —
2
SSI_TXD —
2
SSI_RXD —
— —
— —
— —
— —
MCF5329 Reference Manual, Rev 3
MCF5327
196
MAPBGA
I/O EVDD —
I EVDD —
O EVDD —
I EVDD —
O EVDD —
I/O EVDD —
I/O EVDD —
I/O EVDD E3
I/O EVDD E4
O EVDD P10
O EVDD L11
O EVDD —
O EVDD N10
I EVDD L10
O EVDD M10
I EVDD C9
O EVDD D9
O EVDD A9
I EVDD A10
I EVDD P13
O EVDD N12
O EVDD P12
I EVDD P11
MCF53281
MCF5328
MCF5329
256
256
MAPBGA
MAPBGA
G3 G3
— G2
— G1
G2 —
G1 —
— F3
— F2
F3 —
F2 —
T12 T12
T13 T13
P11 P11
R12 R12
N12 N12
P12 P12
D11 D11
E10 E10
E11 E11
E12 E12
R15 R15
T15 T15
T14 T14
R14 R14
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