Freescale Semiconductor MCF5329 Reference Manual page 246

General Purpose I/O Module
Address: 0xFC0A_401E (PDDR_QSPI)
7
R 0
W
Reset: 0
Figure 13-13. Port QSPI Data Direction Register (PDDR_QSPI)
Address: 0xFC0A_4019 (PDDR_CS)
7
R 0
W
Reset: 0
Address: 0xFC0A_4016 (PDDR_SSI)
7
R 0
W
Reset: 0
Figure 13-15. Port SSI Data Direction Register (PDDR_SSI)
Address: 0xFC0A_4021 (PDDR_LCDDATAH)
7
R 0
W
Reset: 0
Figure 13-16. Port LCDDATAH Data Direction Register (PDDR_LCDDATAH)
Address: 0xFC0A_4024 (PDDR_LCDCTLH)
7
R 0
W
Reset: 0
Figure 13-17. Port LCDCTLH Data Direction Register (PDDR_LCDCTLH)
13-18
6 5
0
0 0
6 5
0
0 0
Figure 13-14. Port CS Data Direction Register (PDDR_CS)
6 5
0 0
0 0
6 5
0 0
0 0
6 5
0 0
0 0
MCF5329 Reference Manual, Rev 3
4 3 2
PDDR_QSPI
0 0 0
4 3 2
PDDR_CS
0 0 0
4 3 2
PDDR_SSI
0 0 0
4 3 2
0 0 0
0 0 0
4 3 2
0 0 0
0 0 0
Access: User read/write
1 0
0 0
Access: User read/write
1 0
0
0 0
Access: User read/write
1 0
0 0
Access: User read/write
1 0
PDDR_LCDDATAH
0 0
Access: User read/write
1 0
0
PDDR_
LCDCTLH
0 0
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