Freescale Semiconductor MCF5329 Reference Manual page 263

Field
7–6 Reserved, should be cleared
5–4 SD_CLK mode select control. These bit fields control the strength of the FlexBus upper data pins.
MSCR_ 00 Half strength 1.8V Mobile DDR.
SDCLKB 01 Open drain.
10 Full strength 1.8V Mobile DDR.
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.
3–2 SD_CLK mode select control. These bit fields control the strength of the FlexBus lower data pins.
MSCR_ 00 Half strength 1.8V Mobile DDR.
SDCLK 01 Open drain.
10 Full strength 1.8V Mobile DDR.
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.
1–0 SD_A10, SD_CAS, SD_CKE, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS, SD_WE mode select control.
MSCR_ These bit fields control the strength of the FlexBus address and control pins.
SDRAM 00 Half strength 1.8V Mobile DDR.
01 Open drain.
10 Full strength 1.8V Mobile DDR.
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.
13.3.8 Drive Strength Control Registers (DSCR_x)
The drive strength control registers set the output pin drive strengths. All drive strength control registers
are read/write.
Register (DSCR_x)
DSCR_I2C
DSCR_PWM
DSCR_FEC
DSCR_QSPI
DSCR_TIMER
DSCR_SSI
DSCR_LCD
DSCR_DEBUG
DSCR_IRQ
Freescale Semiconductor
Table 13-22. MSCR_SDRAM Field Descriptions
Description
I2C_SDA and I2C_SCL
PWM[7,5,3,1]
FEC_MDC and FEC_MDIO
QSPI_PCS[2:0], QSPI_SCK, QSPI_DIN, and QSPI_DOUT
DT3IN, DT2IN, DT1IN, and DT0IN
SSI_MCLK, SSI_BCLK, SSI_RXD, and SSI_TXD
LCD_D[17:0], ACD/OE, CLS, CONTRAST, FLM/SYNC, LP/VSYNC,
LSCLK, PS, REV, and SPL_SPR.
PSTCLK, PST[3:0], DDATA[3:0], ALLPST, and DSO
IRQ[7:1]
MCF5329 Reference Manual, Rev 3
Pins Affected
General Purpose I/O Module
13-35