Freescale Semiconductor MCF5329 Reference Manual page 735

31.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n
and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation,
as described in Section 31.4.1.2.1, "Internal Bus Clock Baud
Address: 0xFC06_0018 (UBG10)
0xFC06_4018 (UBG11)
0xFC06_8018 (UBG12)
7
R
W
Reset: 0
Figure 31-13. UART Baud Rate Generator Registers (UBG1n)
Address: 0xFC06_001C (UBG20)
0xFC06_401C (UBG21)
0xFC06_801C (UBG22)
7
R
W
Reset: 0
Figure 31-14. UART Baud Rate Generator Registers (UBG2n)
The minimum value loaded on the concatenation of UBG1n with UBG2n is
0x0002. The UBG2n reset value of 0x00 is invalid and must be written to
before the UART transmitter or receiver are enabled. UBG1n and UBG2n
are write-only and cannot be read by the CPU.
31.3.12 UART Input Port Register (UIPn)
The UIPn registers show the current state of the UnCTS input.
Address: 0xFC06_0034 (UIP0)
0xFC06_4034 (UIP1)
0xFC06_8034 (UIP2)
7
R 1
W
Reset: 1
Freescale Semiconductor
6 5 4
Divider MSB
0 0 0
6 5 4
Divider LSB
0 0 0
NOTE
6 5 4
1 1 1
1 1 1
Figure 31-15. UART Input Port Registers (UIPn)
MCF5329 Reference Manual, Rev 3
Rates."
Access: User write-only
3 2 1
0 0 0
Access: User write-only
3 2 1
0 0 0
Access: User read-only
3 2 1
1 1 1
1 1 1
UART Modules
0
0
0
0
0
CTS
1
31-15