Overview - Freescale Semiconductor MCF5329 Reference Manual

General Purpose I/O Module
13.4 Functional Description
13.4.1

Overview

Initial pin function is determined during reset configuration. The pin assignment registers allow the user
to select among various primary functions and general purpose I/O after reset. Most pins are configured
as GPIO by default. The notable exceptions to this are external bus control pins, address/data pins, and
chip select pins. These pins are configured for their primary functions after reset.
Every GPIO pin is individually configurable as an input or an output via a data direction register
(PDDR_x). Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x)
to monitor and control the state of its pins. Data written to a PODR_x register is stored and then driven to
the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the
corresponding pins. Reading a PPDSDR_x register returns the current state of the corresponding pins
when configured as general purpose I/O, regardless of whether the pins are inputs or outputs.
Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing
individual bits in the PODR_x register. Initial pin output drive strength is determined during reset
configuration. The DSCR_x registers allow the pin drive strengths to be configured on a per-function basis
after reset.
13.4.2 Port Digital I/O Timing
Input data on all pins configured as general purpose input is synchronized to the rising edge of the bus
clock, FB_CLK, as shown in
FB_CLK
Input
Pin
Register
Pin Data
Data written to the PODR_x register of any pin configured as a general purpose output is immediately
driven to its respective pin, as shown in
13-38
Figure 13-52.
Figure 13-52. General Purpose Input Timing
Figure 13-53.
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor