Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

— HMAC—Hashed message authentication can be used with the SHA-1 or MD5 algorithm
defined in FIPS 198.
— EHMAC—Enhanced Hashed message authentication can only be used with the SHA-1
algorithm.
33.2

Memory Map/Register Definition

Address
0xEC08_0000 MDHA Mode Register (MDMR)
0xEC08_0004 MDHA Control Register (MDCR)
0xEC08_0008 MDHA Command Register (MDCMR)
0xEC08_000C MDHA Status Register (MDSR)
0xEC08_0010 MDHA Interrupt Status Registers (MDISR)
0xEC08_0014 MDHA Interrupt Mask Registers (MDIMR)
0xEC08_001C MDHA Data Size Register (MDDSR)
0xEC08_0020 MDHA Input FIFO (MDIN)
0xEC08_0030 MDHA Message Digest A0 Register (MDA0)
0xEC08_0034 MDHA Message Digest B0 Register (MDB0)
0xEC08_0038 MDHA Message Digest C0 Register (MDC0)
0xEC08_003C MDHA Message Digest D0 Register (MDD0)
0xEC08_0040 MDHA Message Digest E0 Register (MDE0)
0xEC08_0044 MDHA Message Data Size Register (MDMDS)
0xEC08_0070 MDHA Message Digest A1 Register (MDA1)
0xEC08_0074 MDHA Message Digest B1 Register (MDB1)
0xEC08_0078 MDHA Message Digest C1 Register (MDC1)
0xEC08_007C MDHA Message Digest D1 Register (MDD1)
0xEC08_0080 MDHA Message Digest E1 Register (MDE1)
1
Accesses to reserved address locations have no effect and result in a cycle termination transfer error.
33.2.1 MDHA Mode Register (MDMR)
The MDMR stores the current processing mode. It can be written before a hashing operation begins. After
the hashing operation has begun, an error is generated if the register is written. This register is reset only
via a hardware or software reset.
Freescale Semiconductor
Table 33-1. MDHA Module Memory Map
Register
MCF5329 Reference Manual, Rev 3
Message Digest Hardware Accelerator (MDHA)
Width
1
Access Reset Value
(bits)
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 W 0x0000_0000
32 R 0x0000_8408
32 R 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 W 0x0000_0000
32 R/W 0x0123_4567
32 R/W 0x89AB_CDEF
32 R/W 0xFEDC_BA98
32 R/W 0x7654_3210
32 R/W 0xF0E1_D2C3
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
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