Freescale Semiconductor MCF5329 Reference Manual page 339

other CSCRs. FB_CS0 allows address decoding for an external device to serve as the boot memory before
system initialization and configuration are completed.
Address: 0xFC00_8008 (CSCR0)
0xFC00_8014 (CSCR1)
0xFC00_8020 (CSCR2)
0xFC00_802C (CSCR3)
0xFC00_8038 (CSCR4)
0xFC00_8044 (CSCR5)
31 30
R
W
Reset: CSCR0 0 0
Reset: CSCR1–5 0 0
15 14
R
W
Reset: CSCR0
1 1
Reset: CSCR1–5
0 0
Field
31–26 Secondary wait states. The number of wait states inserted before an internal transfer acknowledge is generated for
SWS a burst transfer except for the first termination, which is controlled by the wait state count. The secondary wait state
is used only if the SWSEN bit is set. Otherwise, the WS value is used for all burst transfers.
25–24 Reserved, must be cleared
23 Secondary wait state enable.
SWSEN 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers.
1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer
secondary terminations.
22 Reserved, must be cleared
21–20 Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and
ASET attributes. The address and attributes are considered valid at the same time FB_TS asserts.
00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
01 Assert FB_CSn on second rising clock edge after address is asserted.
10 Assert FB_CSn on third rising clock edge after address is asserted.
11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
Freescale Semiconductor
29 28 27 26 25
0
SWS
0 0 0 0 0
0 0 0 0 0
13 12 11 10 9
WS SBM
[DRAM
1 1 1 1
SEL]
[DRAM
0 0 0 0
SEL]
Figure 17-3. Chip-Select Control Registers (CSCRn)
Table 17-5. CSCRn Field Descriptions
MCF5329 Reference Manual, Rev 3
24 23 22
0 0
SWSEN
0 0 0
0 0 0
8 7 6
AA PS
1 D4 D3
1 0 0
Description
FlexBus
Access: User
read/write
21 20 19 18 17
ASET RDAH WRAH
1 1 1 1 1
0 0 0 0 0
5 4 3 2 1
0 0
BEM BSTR BSTW
1 0 0 0 0
1 0 0 0 0
16
1
0
0
0
0
0
17-7