Freescale Semiconductor MCF5329 Reference Manual page 132

Cache
Way 0
Set 0
Set 1
•
•
•
Set 254
Set 255
TAG
Where:
TAG—20-bit address tag
V—Valid bit for line
M—Modified bit for line
5.3.1.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified
As shown in Table 5-4, a cache line is always in one of three states: invalid, valid-unmodified (often
referred to as exclusive), or valid-modified.
V M
0 x Invalid. Invalid lines are ignored during lookups.
1 0 Valid, not modified. Cache line has valid data that matches system memory.
1 1 Valid, modified. Cache line contains most recent data, data at system memory location is stale.
A valid line can be explicitly invalidated by executing a CPUSHL instruction.
5.3.1.2 Cache at Start-Up
As Figure 5-5 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines
even though the cache may not contain the appropriate data for start up. Because reset and power-up do
not invalidate cache lines automatically, the cache should be cleared explicitly by setting CACR[CINVA]
before the cache is enabled (B).
After the entire cache is flushed, cacheable entries are loaded first in way 0. If way 0 is occupied, the
cacheable entry is loaded into the same set in way 1, as shown in
in detail in Section 5.3, "Functional
5-6
Way 1
• •
• •
• •
Line
Cache Line Format
V M Longword 0
Figure 5-4. Data Cache Organization and Line Format
Table 5-4. Valid and Modified Bit Settings
Description."
MCF5329 Reference Manual, Rev 3
Way 2
•
•
•
Longword 1 Longword 2
Description
Figure 5-5 (D). This process is described
Way 3
•
•
•
Longword 3
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