Lcdc Horizontal Configuration Register (Lcd_Hcr) - Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Liquid Crystal Display Controller (LCDC)
22.3.8

LCDC Horizontal Configuration Register (LCD_HCR)

The horizontal configuration register defines the horizontal sync pulse timing. For detailed settings, please
refer to the panel's data sheet.
Address: 0xFC0A_C01C (LCD_HCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
H_WIDTH
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-9. LCD Horizontal Configuration Register (LCD_HCR)
Field
31–26
Horizontal sync pulse width. Specifies the number of LCD_LSCLK periods that LCD_HSYNC is activated. The
H_WIDTH
active time is equal to (H_WIDTH + 1) of the LCD_LSCLK periods.
25–16
Reserved, must be cleared.
15–8
Wait between LCD_OE and LCD_HSYNC. In TFT mode, this field specifies the number of LCD_LSCLK periods
H_WAIT_1
between the end of LCD_OE signal and the beginning of the LCD_HSYNC. Total delay time equals
(H_WAIT_1 + 1) of LCD_LSCLK periods.
In CSTN mode, H_WAIT_1 specifies the number of LCD_LSCLK periods between the last display data and the
beginning of the LCD_HSYNC signal. Total delay time equals (H_WAIT_1 + 1) of LCD_LSCLK periods.
7–0
Wait between LCD_HSYNC and start of next line. In TFT mode, this field specifies the number of LCD_LSCLK
H_WAIT_2
periods between the end of LCD_HSYNC and the beginning of the LCD_OE signal. Total delay time equals
(H_WAIT_2 + 3).
In CSTN mode, H_WAIT_2 specifies the number of LCD_LSCLK periods between the end of LCD_HSYNC and
the first display data in each line. Total delay time equals (H_WAIT_2 + 2) of LCD_LSCLK periods.
22.3.9
LCDC Vertical Configuration Register (LCD_VCR)
The vertical configuration register defines the vertical sync pulse timing. For detailed settings, please refer
to the panel's data sheet.
Address: 0xFC0A_C020 (LCD_VCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
V_WIDTH
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-10. LCD Vertical Configuration Register (LCD_VCR)
22-12
0 0 0 0 0 0 0 0 0 0
Table 22-11. LCD_HCR Field Descriptions
Description
0 0 0 0 0 0 0 0 0 0
MCF5329 Reference Manual, Rev 3
Access: User read/write
8
7
6
5
H_WAIT_1
H_WAIT_2
Access: User read/write
8
7
6
5
V_WAIT_1
V_WAIT_2
Freescale Semiconductor
4
3
2
1
0
4
3
2
1
0

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