Move Instruction Execution Times - Freescale Semiconductor MCF5329 Reference Manual

ColdFire Core
4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in Table 3-11.
3.3.5.2

MOVE Instruction Execution Times

Table 3-12 lists execution times for MOVE.{B,W} instructions;
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
ET with {<ea> = (d16,PC)}
ET with {<ea> = (d8,PC,Xi*SF)}
The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w
and xxx.l.
Source
Rx
Dy 1(0/0)
Ay 1(0/0)
(Ay) 4(1/0)
(Ay)+ 4(1/0)
-(Ay) 4(1/0)
(d16,Ay) 4(1/0)
(d8,Ay,Xi*SF) 5(1/0)
xxx.w 4(1/0)
xxx.l 4(1/0)
3-24
Table 3-11. Misaligned Operand References
address[1:0] Size
01 or 11 Word
01 or 11 Long
10 Long
NOTE
Table 3-12. MOVE Byte and Word Execution Times
(Ax) (Ax)+
1(0/1) 1(0/1)
1(0/1) 1(0/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
5(1/1) 5(1/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
MCF5329 Reference Manual, Rev 3
Bus Additional
Operations C(R/W)
Byte, Byte 2(1/0) if read
1(0/1) if write
Byte, Word, 3(2/0) if read
Byte 2(0/2) if write
Word, Word 2(1/0) if read
1(0/1) if write
Table 3-13 lists timings for MOVE.L.
equals ET with {<ea> = (d16,An)}
equals ET with {<ea> = (d8,An,Xi*SF)}
Destination
-(Ax) (d16,Ax)
1(0/1) 1(0/1)
1(0/1) 1(0/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
4(1/1) 4(1/1)
5(1/1) —
4(1/1) —
4(1/1) —
(d8,Ax,Xi*SF) xxx.wl
2(0/1) 1(0/1)
2(0/1) 1(0/1)
5(1/1)) 4(1/1)
5(1/1)) 4(1/1)
5(1/1)) 4(1/1)
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