Freescale Semiconductor MCF5329 Reference Manual page 541

Address: 0xFC0A_C040 (LCD_ISR)
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R
0 0 0
W
Reset 0 0 0
Field
31–8 Reserved, must be cleared.
7 Graphic window underrun error. Indicates whether the LCDC FIFO in the graphic window plane has hit an underrun
GWUDR condition. This is when the data output rate is faster than the data input rate to the FIFO of the graphic window plane.
Underrun can cause erroneous data output to LCD_D. The LCD_D data output rate must be adjusted to prevent
this error.
0 Interrupt has not occurred.
1 Interrupt has occurred.
6 Graphic window error response interrupt. Indicates whether the LCDC has issued a read data request in graphic
GWERR window and has received a bus error. It is cleared by reading the status register, at power on reset, or when the
LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
5 Graphic window end-of-frame interrupt. Indicates whether the end of graphic window has been reached. It is
GWEOF cleared by reading the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
4 Graphic window beginning-of-frame interrupt. Indicates whether the beginning of the graphic window has been
GWBOF reached. It is cleared by reading the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
3 Underrun error interrupt. Indicates whether the LCDC FIFO has hit an underrun condition. This is when the data
UDR output rate is faster than the data input rate to the FIFO. Underrun can cause erroneous data output to LCD_D. The
LCD_D data output rate must be adjusted to prevent this error.
0 Interrupt has not occurred.
1 Interrupt has occurred.
2 Error response interrupt. Indicates whether the LCDC has issued a read data request and has received a bus error.
ERR It is cleared by reading the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
Freescale Semiconductor
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
Figure 22-19. LCD Interrupt Status Register (LCD_ISR)
Table 22-20. LCD_ISR Field Descriptions
MCF5329 Reference Manual, Rev 3
Liquid Crystal Display Controller (LCDC)
24 23 22 21
0 0 0 0
0 0 0 0
8 7 6 5
GW GW GW
0
UDR ERR EOF
0 0 0 0
Description
Access: User read-only
20 19 18 17
0 0 0 0
0 0 0 0
4 3 2 1
GW
UDR ERR EOF
BOF
0 0 0 0
16
0
0
0
BOF
0
22-21