Functional Description - Freescale Semiconductor MCF5329 Reference Manual

Algorithm
/Mode
AES-ECB
AES-CBC
DES-CTR
AES-CTR
1
Must be written at start of new message
The value written to the IV/Nonce registers is replaced with the running initialization vector, IV, (CBC
mode) or running counter (CTR mode) after processing begins. If any context registers are read prior to
the SKSR[DONE] bit being set, an early read error, SKESR[ERE], is generated and an interrupt request is
sent to the interrupt controller (if ERE is not masked).
Address: 0xEC08_4070 + 4×(n-1), where n=1–11 (SKCn)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
35.3

Functional Description

At the top level, the SKHA consists of seven functional blocks: The input FIFO, the output FIFO, transmit
FIFO interface, receive FIFO interface, internal bus interface, top control and the SKHA logic.
Freescale Semiconductor
Table 35-8. SKHA Context Register Definitions
SKHA Context Register n (32-bits each)
1 2 3 4 5
— — — — —
1
IV —
1
Counter — — —
1
Counter —
Figure 35-19. SKHA Context Registers (SKCn)
MCF5329 Reference Manual, Rev 3
Symmetric Key Hardware Accelerator (SKHA)
6 7 8 9 10
— — — — —
— — — — —
— — — — —
— — — — —
9 8
Key n
11 12
— —
— —
— —
— —
Access: User read/write
7 6 5 4 3 2 1 0
35-15