Freescale Semiconductor MCF5329 Reference Manual page 610

Synchronous Serial Interface (SSI)
Field
15 Receive data ready 1. Only valid in two-channel mode. Indicates new data is available for the processor to read.
RDR1
Rx FIFO1
Enabled
Disabled
Rx FIFO1
Enabled
Disabled
14 Receive data ready 0. Similar description as RDR1 but pertains to Rx FIFO 0 and it is not necessary to be in
RDR0 two-channel mode for this bit to be set.
0 No new data for core to read
1 New data for core to read
13 Transmit data register empty 1. Only valid in two-channel mode. Indicates that data needs to be written to the SSI.
TDE1
Tx FIFO1
Enabled
Disabled
Tx FIFO1
Enabled
Disabled
24-16
Table 24-8. SSI_ISR Field Descriptions (continued)
Required conditions
• SSI_IER[RIE] set
• SSI_IER[RFF1] set
• SSI_IER[RIE] set
• SSI_IER[RDR1] set
RDR1 is set when
• Rx FIFO1 loaded
with new value
• SSI_RX1 loaded
with new value
Required conditions
• SSI_IER[TIE] set
• SSI_IER[TDE1] set
• SSI_IER[TIE] set
• SSI_IER[TDE1] set
TDE1 is set when
• At least one empty slot in Tx
FIFO1
• SSI_TX1 data transferred to
TXSR
MCF5329 Reference Manual, Rev 3
Description
Receive data 1 interrupt
Trigger
• SSI_ISR[RFF1] sets
• SSI_RX1 loaded with new value
RDR1 is cleared during
any of the following
• Rx FIFO1 is empty
• SSI reset
• POR reset
• SSI_RX1 is read
• SSI reset
• POR reset
Transmit data 1 interrupt
Trigger
• SSI_ISR[TDE1] sets
• SSI_TX1 data transferred to
TXSR
TDE1 is cleared when
any of the following occur
• Tx FIFO1 is full
• SSI reset
• POR reset
• SSI_TX1 is written
• SSI reset
• POR reset
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