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Symmetric Key Hardware Accelerator (SKHA)
Address
0xEC08_403C SKHA Key Data Register 4 (SKKDR4)
0xEC08_4040 SKHA Key Data Register 5 (SKKDR5)
0xEC08_4044 SKHA Key Data Register 6 (SKKDR6)
0xEC08_4070 SKHA Context 1 (SKC1)
0xEC08_4074 SKHA Context 2 (SKC2)
0xEC08_4078 SKHA Context 3 (SKC3)
0xEC08_407C SKHA Context 4 (SKC4)
0xEC08_4080 SKHA Context 5 (SKC5)
0xEC08_4084 SKHA Context 6 (SKC6)
0xEC08_4088 SKHA Context 7 (SKC7)
0xEC08_408C SKHA Context 8 (SKC8)
0xEC08_4090 SKHA Context 9 (SKC9)
0xEC08_4094 SKHA Context 10 (SKC10)
0xEC08_4098 SKHA Context 11 (SKC11)
35.2.1
SKHA Mode Register (SKMR)
The SKMR is used to select the cipher algorithm, direction, and cipher mode as shown in
the mode is modified during message processing, the SKESR[RM] bit is set. The mode may be modified
after the module has completed processing, SKSR[DONE] is set.
If reserved bits or undefined modes are set, a mode error is generated.
Address: 0xEC08_4000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
35-6
Table 35-1. SKHA Memory Map (continued)
Register
NOTE
Figure 35-8. SKHA Mode Register (SKMR)
MCF5329 Reference Manual, Rev 3
Width
Access Reset Value
(bits)
32
W
0x0000_0000
32
W
0x0000_0000
32
W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
32
R/W
0x0000_0000
Access: User read/write
9
8
7
6
5
0 0 0
CTRM
DKP
0
0 0 0 0 0
Freescale Semiconductor
Section/Page
35.2.10/35-13
35.2.10/35-13
35.2.10/35-13
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Figure
35-8. If
4
3
2
1
0
CM DIR ALG
0
0 0
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