Freescale Semiconductor MCF5329 Reference Manual page 909

Table B-2. MCF5329RM Rev 1 to Rev. 2 Changes (continued)
Chapter
Crossbar Corrected first sentence in XBS_PRSn[M3] bit description from "Master 5 (FEC1) priority." to "Master 3 (FEC1)
Switch priority."
Corrected last part of XBS_CRSn[RO] = 1 bit setting from "(attempted writes have no effect and result in a bus
error response)." to "(attempted writes have no effect on the registers and result in a bus error response)."
Corrected XBS_CRSn[PARK] bit description from "Park. Determines which master port this slave port parks on
when..." to "Park. Determines which master port the current slave port parks on when..."
GPIO Table 13-1/Page 13-4: Change D[31:0] signal direction from output (O) to input/output (I/O).
Table 13-1/Page 13-4: Change MCF5327 196 MAPBGA ball locations for the following signals:
Corrected DSCR_MISC field description table title. Previously mislabeled as DSCR_I2C.
Interrupt Marked CLMASK values 0x8–0xE as reserved in CLMASKfield description table.
Controller
Added ICR000, ICR100, ICR200 to register addresses and section heading in ICRn
Added verb "exists" to notes in CLMASK and SLMASK sections.
DMA Controller Added second paragraph to Modes of Operation, Normal Mode section.
Added note to TCDn_CSR[BWC] field description.
Freescale Semiconductor
Signal Name
Old Incorrect Location
RCON
D1
D0
OE
R/W
SD_DQS2
PSTCLK
DDATA[3:0] P7, L8, M8, N8
PST[3:0] P8, L9, M9, N9
EVDD E6, E7, F5–F7, H9, J9, J9, K8,
IVDD E5, K5, K10
SD_VDD E8, E9, F8–F10, J6, K6, J7, K7
MCF5329 Reference Manual, Rev 3
Description
MCF5327 196 MAPBGA
New Correct Location
N7
M6
N6
L7
P6
L6
M7
N7, P7, L8, M8
N8, P8, L9, M9
E6, E7, F5–F7, H9, J9, J9, K8,
K9
E5, K5, K10, J10
E8, E9, F8–F10, J5–J7, K7
Revision History
M7
L6
M6
P6
N6
K6
L7
K9, K11
section.
B-7