Freescale Semiconductor MCF5329 Reference Manual page 387

Table 18-13. Mode Register Field Descriptions (continued)
Field
A3 Burst type.
BT 0 Sequential
1 Interleaved. This setting should not be used because the SDRAMC does not support interleaved bursts.
A2–A0 Burst length. Determines the number of column locations that are accessed for a given
BLEN 000 One. This setting is not valid for DDR.
001 Two
010 Four
011 Eight
Else Reserved
18.5.1.6.2 Extended Mode Register Definition
Figure 18-11 shows the extended-mode register used by DDR SDRAMs. This is the SDRAM's extended
mode register, not the SDRAMC's mode/extended-mode register (SDMR) defined in
"SDRAM Mode/Extended Mode Register
BA1 BA0
Field 0 1
Field
BA1–BA0 Bank address. These must be set to 01 to select the extended mode register.
A11–A1 Option. These bits are not defined by the DDR specification. Each DDR SDRAM manufacturer can use these bits to
OPTION implement optional features. Check with the SDRAM manufacturer to determine if any optional features have been
implemented. For normal operation all bits must be cleared.
A0 Delay locked loop. Controls enabling of the delay locked loop circuitry used for DDR timing.
DLL 0 Enabled
1 Disabled
18.5.1.7 Auto-Refresh Command (REF)
The memory controller issues auto-refresh commands according to the SDCR[REF_CNT] value. Each
time the programmed refresh interval elapses, the memory controller issues a
a REF command.
If a memory access is in progress at the time the refresh interval elapses, the memory controller schedules
the refresh after the transfer finishes; the interval timer continues counting so the average refresh rate is
constant.
After REF command, the SDRAM is in an idle state and waits for an
Freescale Semiconductor
(SDMR)." Refer to device data sheet for detailed description.
A11 A10 A9 A8
Figure 18-11. Extended Mode Register
Table 18-14. Extended-Mode Register Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
A7 A6 A5 A4
OPTION
Description
command.
ACTV
SDRAM Controller (SDRAMC)
or command.
READ WRITE
Section 18.4.1,
A3 A2 A1 A0
DLL
command followed by
PALL
18-25