Descriptor Individual Upper Address Register (Iaur); Descriptor Individual Lower Address Register (Ialr) - Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Fast Ethernet Controller (FEC)
Field
31–16
Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001.
OPCODE
15–0
Pause Duration field used in PAUSE frames.
PAUSE_DUR

19.4.15 Descriptor Individual Upper Address Register (IAUR)

IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the destination address (DA) field of receive
frames with an individual DA. This register is not reset and you must initialize it.
Address: 0xFC03_0118
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 19-15. Descriptor Individual Upper Address Register (IAUR)
Field
31–0
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
IADDR1
address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.

19.4.16 Descriptor Individual Lower Address Register (IALR)

IALR contains the lower 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the DA field of receive frames with an individual
DA. This register is not reset and you must initialize it.
Address: 0xFC03_011C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 19-16. Descriptor Individual Lower Address Register (IALR)
Field
31–0
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
IADDR2
address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
19-20
Table 19-18. OPD Field Descriptions
Description
IADDR1
Table 19-19. IAUR Field Descriptions
Description
IADDR2
Table 19-20. IALR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Access: User read/write
8
7
6
5
4
3
2
1
0
Access: User read/write
8
7
6
5
4
3
2
1
0
Freescale Semiconductor

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