Freescale Semiconductor MCF5329 Reference Manual page 252

General Purpose I/O Module
13.3.5.1 External Bus Control Pin Assignment Register (PAR_BUSCTL)
The PAR_BUSCTL register controls the functions of the external bus control signal pins.
Address: 0xFC0A_4052 (PAR_BUSCTL)
7
R
PAR_OE
W
Reset: 1
Figure 13-34. External Bus Control Pin Assignment Register (PAR_BUSCTL)
Field
7 0 OE pin configured for GPIO
PAR_OE 1 OE pin configured for external bus OE function
6 0 TA pin configured for GPIO
PAR_TA 1 TA pin configured for external bus TA function
5 0 R/W pin configured for GPIO
PAR_RWB 1 R/W pin configured for external bus read/write function
4–3 00 TS pin configured for GPIO
PAR_TS 01 Reserved
10 TS pin configured for DMA acknowledge 0 function
11 TS pin configured for external bus TS function
2–0 Reserved, should be cleared.
13.3.5.2 Byte Enable Pin Assignment Register (PAR_BE)
The PAR_BE register controls the functions of the byte enable pins.
Address: 0xFC0A_4054 (PAR_BE)
7
R 0
W
Reset: 0
Figure 13-35. Byte Enable Pin Assignment Register (PAR_BE)
13-24
6 5
PAR_TA PAR_RWB
1 1
Table 13-8. PAR_BUSCTL Field Descriptions
6 5
0 0
0 0
MCF5329 Reference Manual, Rev 3
4 3 2
0
PAR_TS
1 1 0
Description
4 3 2
0
PAR_BE
0 1 1
Access: User read/write
1 0
0 0
0 0
Access: User read/write
1 0
1 1
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