Freescale Semiconductor MCF5329 Reference Manual page 629

To summarize, the network mode transmitter generates interrupts every enabled time slot and requires the
processor to respond to each enabled time slot. These responses may be:
• Write data in data register to enable transmission in the next time slot.
• Configure the time slot register to disable transmission in the next time slot (unless the time slot is
already masked by the SSI_TMASK register bit).
• Do nothing—transmit underrun occurs at the beginning of the next time slot and the previous data
is re-transmitted.
In two channel operation, both channels (data registers, FIFOs, interrupts, and DMA requests) operate in
the same manner, as described above. The only difference is interrupts related to the second channel are
generated only if this mode of operation is selected (TDE1 is low by default).
24.4.1.2.2 Network Mode Receive
The receiver portion of the SSI is enabled when both the SSI_CR[SSI_EN and RE] bits are set. However,
the receive enable only takes place during that time slot if RE is enabled before the second to last bit of the
word. If the RE bit is cleared, the receiver is disabled at the end of the current frame. The SSI module is
capable of finding the start of the next frame automatically. When the word is completely received, it is
transferred to the SSI_RX register, which sets the RDR bit. This causes a receive interrupt to occur if the
the RIE bit is set. The second data word (second time slot in the frame) begins shifting in immediately after
the transfer of the first data word to the SSI_RX register. The processor has to read the data from the
receive data register (which clears RDR) before the second data word is completely received (ready to
transfer to RX data register) or a receive overrun error occurs (the ROE bit is set).
An interrupt can occur after the reception of each enabled data word or the user can poll the RDR flag. The
processor response can be:
• Read RX and use the data.
• Read RX and ignore the data.
• Do nothing—the receiver overrun exception occurs at the end of the current time slot.
For a continuous clock, the optional frame sync output and clock output
signals are not affected, even if transmitter or receiver is disabled. TE and
RE do not disable the bit clock or the frame sync generation. To disable the
bit clock and the frame sync generation, the SSI_CR[SSI_EN] bit can be
cleared or the port control logic external to the SSI (e.g. GPIO) can be
reconfigured.
In two channel operation, both the channels (data registers, FIFOs, interrupts, and DMA requests) operate
in the same manner as described above. The only difference is second channel interrupts are generated only
in this mode of operation.
Figure 24-30 shows the transmitter and receiver timing for an 8-bit word with continuous clock, FIFO
disabled, three words per frame sync in network mode.
The transmitter repeats the value 0x5E because of an underrun condition.
Freescale Semiconductor
NOTE
NOTE
MCF5329 Reference Manual, Rev 3
Synchronous Serial Interface (SSI)
24-35