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Appendix A
Register Memory Map Quick Reference
A.1
Register Memory Map
Table A-1
illustrates the overall device memory map.
each peripheral within the two peripheral controllers space. Each module is then detailed in
through
Table
A-34.
Table A-4
not accessible through the memory map but are included here for completeness.
Address Range
0x0000_0000–0x3FFF_FFFF
0x4000_0000–0x7FFF_FFFF
0x8000_0000–0x8FFF_FFFF
0xC000_0000–0xDFFF_FFFF
0xE000_0000–0xEFFF_FFFF
0xF000_0000–0xFFFF_FFFF
1
See the various tables below or the peripheral chapters for their memory maps. Any unused
space by these peripherals within this memory range is reserved and should not be accessed.
This memory map provides two disjoint regions mapped to the FlexBus
controller to support glueless connections to external memories (e.g., flash
and SRAM) as well as a second space with one (or more) unique
chip-selects that can be used for non-cacheable, non-memory devices
(addresses 0xC000_0000–0xDFFF_FFFF). Additionally, this mapping is
selected because it easily maps into the ColdFire access control registers,
which provide a coarse association between memory addresses and their
attributes (e.g., cacheable, non-cacheable). For this device, one possible
configuration defines the default memory attribute as non-chacheable, and
one ACR is then used to identify cacheable addresses, e.g., ADDR[31]=0
identifies the cacheable space.
Freescale Semiconductor
Table A-2
and
Table A-5
summarize the ColdFire core and debug registers, which are
Table A-1. Device Memory Map Overview
Module
FlexBus
SDRAM Controller
Internal SRAM Backdoor
FlexBus
1
On-chip Peripheral Controller 1
1
On-chip Peripheral Controller 0
NOTE
MCF5329 Reference Manual, Rev 3
and
Table A-3
list the base address for
Size
1024 MB
1024 MB
256 MB
512 MB
256 MB
256 MB
Table A-6
A-1
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