Freescale Semiconductor MCF5329 Reference Manual page 913

Table B-2. MCF5329RM Rev 1 to Rev. 2 Changes (continued)
Chapter
LCD Controller Change LCD_SCLK to LCD_LSCLK throughout to be consistent with rest of the reference manual.
Table 22-5/Page 22-5: Add the following note to LCD_SR[XMAX] bit field: "The maximum supported panel size
is 800x600 pixels. Therefore the maximum value for this bit field is 0x32."
Table 22-5/Page 22-5: Add the following note to LCD_SR[YMAX] bit field: "The maximum supported panel size
is 800x600 pixels. Therefore the maximum value for this bit field is 0x258."
Table 22-22/Page 22-22: Add the following note to LCD_GWSR[GW_XMAX] bit field: "The maximum supported
panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x32."
Table 22-22/Page 22-22: Add the following note to LCD_GWSR[GW_YMAX] bit field: "The maximum supported
panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x258."
Section 22.3.23/Page 22-24: Change note to:
The graphics window can only be enabled while the clock to the LCD controller is disabled
(MISCCR[LCDCHEN] is cleared). See
bit. The graphics window can be disabled at any time.
Table 22-10/Page 22-10: In PCD bit description change the note to:
Note: The value of PCD must be set such that the LCD_LSCLK frequency is at least one-third (TFT mode) or
one-fourth (CSTN mode) of the peripheral bus clock (f
is incorrect.
FlexCAN Corrected Interrupt section. There are 19 total FlexCAN interrupts; added 16 individual interrupts per MB.
SSI Changed FIFO size from 8x24 to 8x32.
Changed ACDAT from 19 bits to 20 bits wide (from SSI_ACDAT[18:0] to SSI_ACDAT[19:0])
Figure 24-15/Page 24-15: Correct register name in top of register figure from SISRR to SSI_ISR.
Figure 24-18/Page 24-20: Add R/W RXDIR bit to bit location 5 in SSI_RCR register.
SSI Table 24-11/Page 24-21: Add RXDIR bit to bit location 5 with the following description:
(continued)
Gated clock enable. In synchronous mode, this bit enables gated clock mode.
0 Gated clock mode disabled.
1 Gated clock mode enabled.
Real Time Rescind errata regarding 2HZ/2SEC bitfield name. The interrupt is, in fact, a 2 Hz interrupt.
Clock
Clarified Modes of operation
PWM Corrected the numerical values in the left-aligned and center-aligned examples.
Section 26.2/Page 26-2: Previous errata from revision 0 has crept in: Add a 0x20 offset to all PWM register
addresses in the memory map table. Register addresses should be from 0xFC09_0020 to 0xFC09_0044.
Also fix address for the PWMSDN register description to 0xFC09_0044.
Watchdog Figure 27-1/Page 27-2: Change 8192 divider to 4096.
Timer
Section 27.2.3/Page 27-4: Change 8192 multiplier in equation 20-1 and text below it to 4096. As a result the
maximum timeout frequency changes from 6.71 to 3.36 seconds.
PITs Figure 28-4/Page 28-5: Remove "IPSBAR Offset" from PCNTRn register diagram.
DMA Timers Corrected DTRRn reset value in timer memory map from 0x1111_1111 to 0xFFFF_FFFF.
QSPI Removed mention of QSPI_CS3 throughout as it is not available on this device.
Freescale Semiconductor
Description
Chapter 9, "Chip Configuration Module (CCM),"
section.
MCF5329 Reference Manual, Rev 3
) frequency. Otherwise, the line data (LCD_D)
sys/3
Revision History
for details on this
B-11