Skha Logic Block - Freescale Semiconductor MCF5329 Reference Manual

35.3.4

SKHA Logic Block

This block contains the internal address decoder, addressable registers (key data, key size, data size, mode,
context data, and status), interrupt and error logic, DMA input/output request control, and the core engine
as shown in Figure 35-21.
35.3.4.1 Address Decode Logic
The address decoder translates the internal address to write to the proper SKHA registers.
35.3.4.2 Error Interrupt/Status Logic
This block generates the error interrupt if the host performs an illegal operation. The cause of the error is
flagged in the SKHA error status register
(SKESR, SKESMR)") and an interrupt is triggered to the interrupt controller. If an error occurs, the SKHA
core engine is halted. This prevents the core from continuing operation with invalid data. These error
interrupts may be masked off selectively by setting the appropriate bits in the SKHA error status mask
register (Section 35.2.5, "SKHA Error Status and Mask Registers (SKESR,
35.3.4.3 DMA Request Control
This block is the control for the input and output DMA request signals. It monitors the input and output
FIFO levels and DMA request levels (SKCR[ODMAL & IDMAL]) to determine when a DMA request
should be triggered to the DMA controller.
Freescale Semiconductor
Key Key Size
Registers Register
Address
SKHA
Decoder
Core
Mode
Data Size
Register
Register
Figure 35-21. SKHA Logic Block Diagram
(Section 35.2.5, "SKHA Error Status and Mask Registers
MCF5329 Reference Manual, Rev 3
Symmetric Key Hardware Accelerator (SKHA)
Error Status
Block
In Block
Out Block
Status
Register
DMA Request
Control
SKHA LOGIC
SKESMR)")
To DMA
Controller
35-17