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Chapter 5
Cache
5.1
Introduction
This section describes the cache implementation, including organization, configuration, and coherency. It
describes cache operations and how the cache interfaces with other memory structures.
5.1.1
Overview
This ColdFire processor contains a non-blocking, 16-Kbyte, 4-way set-associative, unified (instruction
and data) cache with a 16-byte line size. The cache improves system performance by providing
low-latency access to the instruction and data pipelines. This decouples processor performance from
system memory performance, increasing bus availability for on-chip DMA or external devices.
shows the organization and integration of the cache.
Control
ColdFire
Processor
Core
Data
Address
The cache supports operation of copyback, write-through, or cache-inhibited modes. A nonblocking cache
services read hits or write hits from the processor while a fill (caused by a cache allocation) is in progress.
As
Figure 5-1
shows, instruction and data accesses use a single bus connected to the cache.
All addresses from the processor to the cache are physical addresses. A cache hit occurs when an address
matches a cache entry. For a read, the cache supplies data to the processor. In write, the processor updates
the cache. If an access does not match a cache entry (misses the cache) or if a write access must be written
Freescale Semiconductor
Cache
Control Logic
Data Array
Directory Array
Data Path
Address Path
Figure 5-1. Unified Cache Organization
MCF5329 Reference Manual, Rev 3
Control
FlexBus
Data
Address
Figure 5-1
External
Bus
Control
Address/
Data
5-1
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