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Chapter 10
Reset Controller Module
10.1
Introduction
The reset controller determines the cause of reset, asserts the appropriate reset signals to the system, and
keeps a history of what caused the reset.
10.1.1
Block Diagram
Figure 10-1
illustrates the reset controller and is explained in the following sections.
10.1.2
Features
Module features include the following:
•
Six sources of reset:
— External
— Power-on reset (POR)
— Core watchdog timer
— On-chip watchdog timer
— Phase locked-loop (PLL) loss of lock
— Software
•
Software-assertable RSTOUT pin independent of chip reset state
•
Software-readable status flags indicating the cause of the last reset
Freescale Semiconductor
RESET
Pin
Power-On
Reset
Core Watchdog
Timer Timeout
Controller
On-chip Watchdog
Timer Timeout
PLL
Loss of Lock
Software
Reset
Figure 10-1. Reset Controller Block Diagram
MCF5329 Reference Manual, Rev 3
RSTOUT
Pin
Reset
To Internal Resets
10-1
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