Freescale Semiconductor MCF5329 Reference Manual page 245

13.3.2 Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port pin drivers when the pins are configured for GPIO. The
PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for
all ports are shown in the figures below.
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x register
configures the corresponding port pin as an output. Clearing any bit in a PDDR_x register configures the
corresponding pin as an input.
Address: 0xFC0A_4017 (PDDR_BUSCTL)
0xFC0A_4018 (PDDR_BE)
0xFC0A_401B (PDDR_FECI2C)
0xFC0A_401F (PDDR_TIMER)
7
R 0
W
Reset: 0
Address: 0xFC0A_4014 (PDDR_FECH)
0xFC0A_4015 (PDDR_FECL)
0xFC0A_401D (PDDR_UART)
0xFC0A_4022 (PDDR_LCDDATAM)
0xFC0A_4023 (PDDR_LCDDATAL)
0xFC0A_4025 (PDDR_LCDCTLL)
7
R
W
Reset: 0
Address: 0xFC0A_401A (PDDR_PWM)
7
R 0
W
Reset: 0
Figure 13-12. Port PWM Data Direction Register (PDDR_PWM)
Freescale Semiconductor
6 5
0 0
0 0
Figure 13-10. Port Data Direction Registers (PDDR_x)
6 5
0 0
Figure 13-11. Port Data Direction Registers (PDDR_x)
6 5
0
0 0
MCF5329 Reference Manual, Rev 3
4 3 2
0
0 0 0
4 3 2
PDDR_x
0 0 0
4 3 2
PDDR_PWM
0 0 0
General Purpose I/O Module
Access: User read/write
1 0
PDDR_x
0 0
Access: User read/write
1 0
0 0
Access: User read/write
1 0
0 0
0 0
13-17