Table of Contents
Advertisement
2
The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It
must stop driving the data bus pins within one FB_CLK cycle after RSTOUT is negated. To prevent contention with
the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become
outputs until at least one FB_CLK cycle after RSTOUT is negated.
3
32-bit port size is not available when DRAMSEL = 0. Defaults to 16-bit mode instead.
9.4.2
PLL Mode Selection
The initial device operating frequency is determined during reset configuration by the D1 pin. The default
configuration with a 16 MHz input clock is 180 MHz for the core and 60 MHz for the internal bus. The
user may choose to increase these frequencies (240 MHz and 80 MHz) by placing the device in limp mode
and reconfiguring the appropriate PLL registers, or asserting D1 during reset configuration.
9.4.3
Oscillator Mode Selection
Use of the internal oscillator can be selected during reset configuration via the D2 pin. By default, the
oscillator is enabled and the PLL is placed in normal mode with a crystal reference. If default configuration
is over-ridden and D2 is asserted, the PLL is placed in normal mode with a external reference and the
internal oscillator is bypassed. After reset is exited, the oscillator mode cannot be changed. See
"Clock Module"
for more details on the available modes.
9.4.4
Boot Device Selection
During reset configuration, the FB_CS0 chip select pin is configured to select an external boot device. In
this case, the V (valid) bit in the CSMR0 register is ignored, and FB_CS0 is enabled after reset. FB_CS0
is asserted for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address
0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from address
0x0000_0004 causes the core to start executing from external memory space decoded by FB_CS0.
9.4.5
Output Pad Strength Configuration
Output pad strength is determined during reset configuration as shown in
the output pad strength configuration can only be changed using the GPIO module. For more information
see
Chapter 13, "General Purpose I/O Module."
Output pads configured for low drive strength
Output pads configured for full drive strength
1
Modifying the default configurations is possible only if the external RCON pin is
asserted low.
Freescale Semiconductor
Table 9-11. Output Pad Driver Strength Selection
Optional Pin Function Selection
MCF5329 Reference Manual, Rev 3
Chip Configuration Module (CCM)
Chapter 7,
Table
9-11. After reset is exited,
1
D5
D5 driven low
D5 driven high
9-11
Advertisement
Table of Contents
